Network-on-Chip Architecture, Optimization, and Design Explorations
Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (No...
Saved in:
| Other Authors: | , , , |
|---|---|
| Format: | Electronic Book Chapter |
| Language: | English |
| Published: |
IntechOpen
2022
|
| Subjects: | |
| Online Access: | DOAB: download the publication DOAB: description of the publication |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems. |
|---|---|
| Physical Description: | 1 electronic resource (110 p.) |
| ISBN: | intechopen.91110 9781839681585 9781839681486 9781839681592 |
| Access: | Open Access |