Network-on-Chip Architecture, Optimization, and Design Explorations
Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (No...
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Other Authors: | Alimi, Isiaka A. (Editor), Aboderin, Oluyomi (Editor), Muga, Nelson J. (Editor), Teixeira, António L. (Editor) |
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Format: | Electronic Book Chapter |
Language: | English |
Published: |
IntechOpen
2022
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Subjects: | |
Online Access: | DOAB: download the publication DOAB: description of the publication |
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