Statistical optimization influence on high permittivity gate spacer in 16nm DG-FinFET device / Ameer F. Rosla ... [et al.]

• Main Authors: Rosla, Ameer F. (Author), Salehuddin, F. (Author), Zain, A.S.M (Author), Kaharudin, K.E (Author), Mohamad, N.R (Author), A.H, Afifah Maheran (Author), Haroon, H. (Author), Razak, H.A (Author), Idris, S.K (Author), Ahmad, I. (Author)
• Format: Book
• Published: Universiti Teknologi MARA, 2022-01.
• Subjects: Article; PeerReviewed
• Online Access: Link Metadata
• Notes: https://ir.uitm.edu.my/id/eprint/60588/1/60588.pdf
• Keywords: Industrial engineering. Management engineering

In this paper, the effect of high permittivity gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET is investigated, with the output responses optimized using L9 orthogonal array (OA) Taguchi method. The determination is done through Signal-to-noise ratio to the effectiveness of the process parameters towards four output responses such as threshold voltage (VTH), drive current (ION), leakage current (IOFF) and Subthreshold Swing (SS). The virtual fabrication of the 16 nm double-gate fin FET was performed using ANTHENA module while the electrical characteristics of the device were simulated using ATLAS module. These two modules were combined with Taguchi method to aid in designing and optimizing the process parameters. The electrical characterization was performed and significant improvement could be seen on the TiO2 and HfO2 material in terms of the ION/IOFF ratio obtained at 4.03106 and 3.61106 respectively for 0.179±12.7% V of VTH. It can be observed that when approaching a higher value of dielectric constant (high-K), the ION increases while the SS and IOFF decreases. As conclusion, the output responses from high-K materials have been proven to meet the minimum requirement by International Technology Roadmap Semiconductor (ITRS) 2013 for high performance Multi-Gate technology for the year 2015.