The effect of gate geometric effect and polysilicon doping on the performance of scaled NMOS / Muhammad Luqman Nurhakim Kamarudin... [et al.]

• Main Authors: Kamarudin, Muhammad Luqman Nurhakim (Author), Abd Rahim, Alhan Farhanah (Author), Mohd Razali, Nurul Syuhadah (Author), Radzali, Rosfariza (Author), Mahmood, Ainorkhilah (Author), Hamzah, Irni Hamiza (Author), Idris, Mohaiyedin (Author), Mohamed, Mohamed Fauzi Packeer (Author)
• Format: Book
• Published: Universiti Teknologi MARA Cawangan Pulau Pinang, 2023-03.
• Subjects: Article; PeerReviewed
• Online Access: Link Metadata
• Notes: https://ir.uitm.edu.my/id/eprint/76051/1/76051.pdf
• Keywords: LG Individual institutions; Malaysia; Pulau Pinang; Universiti Teknologi MARA; Asia; TK Electrical engineering. Electronics. Nuclear engineering; Electronics; Apparatus and materials; Semiconductors; Applications of electronics

Insufficiently high doping in polysilicon gates of metal oxide semiconductor field effect transistor (MOSFET) becomes unavoidable due to the demands for low-energy ion implantation and limited annealing conditions to achieve ultra-shallow source and drain junctions. This results in the poly-depletion effect for ultra-thin MOSFET, loss of current drive and shift in the threshold voltage. This problem gets intense when the device is further scaled down for the gate length and thickness of gate oxide. Hence, our current work focuses on the effect of gate geometrical effect and polysilicon gate doping on scaled n-channel MOSFET(NMOS) performance. The NMOS device was constructed using TCAD ATLAS tools from SILVACO software. Six different gate lengths of 0.6 μm, 0.4 μm, 0.2 μm, 60 nm, 40 nm and 20 nm were set, and the n-type doping concentration in the polysilicon gate was varied to 1× 1018, 1× 1020 and 1 × 1021 cm-3 respectively to see their effect on the NMOS I-V and C-V performances. The findings showed that as the gate length is scaled down, the drain current increases, and as the concentration of the polysilicon doping increases, the value of the threshold voltage, VTH decreases. Based on the simulation and data collected, it can be concluded that the optimum concentration of polysilicon doping that can reduce the poly-depletion effect is 1 × 1021 cm-3, and the optimum gate length that can be used to overcome the problem is 20 nm.