InP DHBT-based clock and data recovery circuits for ultra-high-speed optical data links
In this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with 1:2 demultiplexer are developed. The integrated circuits are manufactured using an InP double heterojunction bipolar transistor (DHBT) technology, featuring cut-off frequency values of more than 250 G...
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| Main Author: | |
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| Format: | Electronic Book Chapter |
| Language: | English |
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KIT Scientific Publishing
2006
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| Subjects: | |
| Online Access: | DOAB: download the publication DOAB: description of the publication |
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| Summary: | In this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with 1:2 demultiplexer are developed. The integrated circuits are manufactured using an InP double heterojunction bipolar transistor (DHBT) technology, featuring cut-off frequency values of more than 250 GHz. The outstanding and (to some extent) record achievements throughout the work make an essential contribution to the development of future optical telecommunication networks operating at 80 Gbit/s. |
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| Physical Description: | 1 electronic resource (VI, 167 p. p.) |
| ISBN: | KSP/1000004568 3866440456 |
| Access: | Open Access |